Intel and Micron take the Plunge with Non-volatile 3D XP

Introduction to 3D XP

Intel & Micron have announced an intent to manufacturer 3D Xpoint™ (pronounced as 3D cross-point) non-volatile memory. The abbreviation 3D XP is used in this research. The key characteristics of the 3D XP are:

1. It is bit addressable, the same as DRAM, and unlike NAND flash (block addressable, and requires DRAM in front of it).
2. It is non-volatile, unlike DRAM (which can be protected with capacitors or batteries), and like NAND flash.
3. It is slower than DRAM, and faster than NAND flash.
4. Intel and Micron claim 3D XP “is not significantly impacted by the number of write cycles it can endure.” This would make it more durable than NAND flash, and less durable than DRAM.
5. 3D XP will use the NVMe as the standard for access. Initially 3D XPoint will use PCI Express (PCIe) as its means of connecting to existing computers, as PCIe currently has the fastest bus speed of any peripheral interface.
6. The potential speed of 3D XPoint is higher than PCIe buses. Intel are looking at new ways to mount it using memory buses, which will likely to require an upgraded motherboard architecture with the new Intel Photonics that were pushed out in February 2015 to 2016. And, of course, this gives Intel an opportunity to bundle.
7. Intel and Micron claim that 3D XP is 8-10 time denser than current DRAM using the current nanometer process. (This comparative claim will be determined by comparison to the latest technologies if and when volume shipment of 3D XP is achieved).
8. The references at the end of this research point to 3D XP having a PCM-type architecture (Phase Change Memory).

The speed, density, power consumption and costs of 3D XP compared with DRAM and NAND flash will depend on when 3D XP reaches the marketplace. There are still many challenges to overcome on how to manufacturer this technology, and early shipments are not expected until 2016 and production shipment until 2017/2018. The comparisons given by Intel and Micron in Figure 1 are to current DRAM and flash technologies, not the technologies available in 2018.

The key to its success will be the volume demand for the product, and the ability to justify being used on the lowest nanometer fabrications ahead of the current demand for DRAM, NAND flash and processor chips.

Deployment of 3D XP

In some ways this is back to the future. Early machines (1950-75) used ferrite non-volatile bit-addressable core storage (see Figure 2); the term is still used in “core dumps”. So what are the potential uses of this new technology? What applications and architectures could drive volume demand?

Much as it galls IT professionals, the volume market for NAND flash is the consumer market, with 10 times the volume of enterprise use of flash. Unless 3D XP is significantly cheaper than flash, it will not replace flash in the consumer market for the next decade. That also means it will not replace flash for large scale storage in the enterprise IT market.

That leaves the use of flash as a replacement for DRAM. Here the prospects are much brighter. Assuming it can be made in volume at lower cost than DRAM, 3D XP could be used directly in consumer products where power consumption is important. This could include wearables such as watches and mobile devices, with the caveat that most power consumption is from mobile/WiFi/Bluetooth communication and displays rather than the DRAM in the device. The downside would be a significant rewrite of current OS software to take advantage of non-volatile qualities of 3D XP. This current market is dominated by ARM processors, with almost no Intel participation.

The PC market is declining, and is not sufficient in size to warrant much investment. Gaming PCs and financial modeling systems would be much faster with large-scale DRAM than 3D XP.

One tough business choice that Intel is likely to have to make is whether to provide this technology on ARM processors. Intel have poured billions of dollars into attempting to break into the mobile market, and paid mobile manufacturers large amounts for product placements that have gone nowhere. Will Intel tie 3D XP to its own X86 chips in a last-ditch effort to get into mobile? Can it create an independent ecosystem? The odds for success with this strategy are poor. Depending on the agreement details between Intel and Micron, Micron could be free to go after this space and develop ARM/3D XP processors

The most likely volume market is in ultra-small devices, where the processor, non-volatile memory and sensors can be manufactured in a single microchip. There are definite military use cases of these that could help fund initial developments. However, the time to volume in this new market is likely to be greater than five years.

If these volume cases do not appear, the prospects for 3D XP look less rosy. It would then be a replacement for MRAM technology, produced on older fabs with lower volumes. It would then be a product that filled a gap between DRAM and NAND flash and competed with capacitance protected DRAM.

There may be some value as a faster memory tier between DRAM and flash, but the size of this tier will be constrained by its bit access architecture. It will also come under fire from DRAM/Flash implementations that use DRAM slots deployed as a simple large memory, introduced by companies like Diablo. These deployments and any 3D XP memory bus deployments will need to deploy very fast memory switching fabrics, to allow sharing of data between a network/cluster of servers.

Action Item:

There have only been two successful volume introductions into the marketplace in the last 50 years – DRAM and NAND flash. There has to be a clear volume case with good economics for 3D XP to be able to gain a foothold in consumer products. CIOs, CTOs and enterprise professionals should take a wait and see stance, and monitor the adoption of 3D XP in the consumer and military spaces. If and when there is volume production for 3D XP, enterprise adoption should start about two years later.

References:

A stackable cross point Phase Change Memory, DerChange Kau et al, 2009, Intel Corporation